Sr. Principal Lead Design Verification Engineer

Title: Sr. Principal Lead Design Verification Engineer The Verification Lead will be responsible for taking ownership of the verification a...

Title: Sr. Principal Lead Design Verification Engineer

The Verification Lead will be responsible for taking ownership of the verification architecture and drive the entire verification flow. This is a unique opportunity to be responsible for building the and driving the verification infrastructure from the ground up for High Performance Computing Architecture of RISC-V Multi CPU you subsystems designs.

Responsibilities

• Ownership of the DV environment from concept to closure.
• Develop and optimize the DV flows and oversee regressions.
• Complete ownership of DV closure.
• Mentoring team members
• Work closely with System Design, RTL Design and SW/FW teams.

Required Skills

• Team leadership and mentoring experience.
• Strong communication skills and team player.
• Experience in with constrained-random verification environments
• Experience creating complex verification environment.
• Extensive experience with complex ICs using System Verilog, UVM and SVAs.
• Excellent HDL Debug experience and strong problem-solving skills, specifically within SystemVerilog.
• Development of high-quality re-usable and scalable verification code.
• Script development using Python, Perl or similar language.

Desirable Skills

• Object-oriented programming, data structures, and algorithms.
• Cadence Xcelium or Synopsys VCS.
• Experience in Formal Verification.
• Knowledge of RISC-V HW/SW
• Previous experience verifying Cryptocurrency, HPC or AI/ML products.