The AMS IP team is responsible for developing mixed signal PHY IP for AI and Crypto Currency hardware developed by Canaan. These PHY IP's in...
The AMS IP team is responsible for developing mixed signal PHY IP for AI and Crypto Currency hardware developed by Canaan. These PHY IP's include DDR3,LPDDR3,LPDDR4/x, LPDDR5 PHY, MIPI DPHY 1.2, USB, General Purpose 2.5G PHY and UHS-2 PHY as well as general IO, PLL, DLL and analog IP.
Role and Responsibilities
The team is expanding and looking for a senior engineer to fill the role as senior analog design engineer responsible for architecture and design of high speed PLL's, DLL's and CDR's for DDR, MIPI and General Purpose PHYs. The engineer will be responsible for working with the digital design team, place and route engineer, to write documentation for the IP, architect and develop and simulate and verify the analog solutions for the PHY. Additionally it is expected that the design engineer will work closely with the layout team to direct and verify the layout.
Qualifications and Education Requirements
Experience architecting and designing PLL and DLL solutions that operate at 2.5 - 5GHz in processes at 16n and below.
Experience with CDR design for UHS--II and PCI-Express Gen 1/2
Experience with MIPI (DPHY/CPHY) or DDR DLL & PLL
BSEE required MSEE preferred
10+ years of experience preferred
Experience with Cadence Virtuoso Design Flow
AMS Engineering is distributed between North & South America and China & Taiwan. It is an Independent work environment with focus on communication and an ability to work across many time zones will be a plus.
- provided by Dice